In recent years, the wide voltage range ICs are drawing great attention, which generally have a coverage from near-threshold/sub-threshold region to normal voltage region, and can operate in wide voltage range, so as to meet the high performance or energy-efficiency demands for chips under various loads. However, due to the PVT (Process, Voltage, and Temperature) variation and the problem of circuit aging, certain timing margins have to be preserved during circuit design to insure the proper operation of the circuit under the worst-case scenario, which leads to the degradation of performance and energy-efficiency. Since these adverse timing variations seldom occur simultaneously or even not at all, making the operating voltages too conservative and the chip performance far from optimal.
To achieve the high performance or energy-efficiency of chip, the timing margins are generally reduced to run the chip under lower voltage or higher frequency, which makes the chip more vulnerable to the critical path timing violation and results to the runtime error. The circuits of the razor structure employ typical online timing detecting method, which lowers the voltage to the limit until the circuit timing errors occur, and utilize in-situ or upper recovery mechanism to recover the chip's correct operating state. The monitoring unit employing these kinds of monitoring method is characterized in that: first, monitoring the timing operation to effectively determine whether there are errors in the circuit timing in one clock cycle; second, maintaining the correct timing results to achieve the error correction in case of timing errors. The monitoring unit consists of two timing units: a normal flip-flop and a shadow latch. During the design, by replacing the traditional flip-flop with the Razor monitoring unit, the timing monitoring and error correction functions for the circuit can be achieved easily. When the circuit is operating properly, the flip-flop in the monitoring unit acts with no difference from traditional flip-flop. But if there are errors in circuit timing, the shadow latch saves the correct timing result, which can be used in error correction of data.
By utilizing the online timing monitoring method to detect the delay variation of the on-chip timing monitoring unit, the PVT condition of the circuit may be obtained. According to this information, the system may make corresponding voltage or frequency adjustments to the target circuit to achieve high performance or energy-efficiency for the chip. The occurrence of errors in the chip indicate the timing violation, which means the timing margin is not enough at this time. To insure the proper operation of the chip, an immediate frequency reduction operation is required to increase the timing margin and address the problem of timing violation. The traditional frequency reduction methods are frequency division and modulating PLL configuration. While the frequency division can achieve immediate frequency reduction, it can only provide integer frequency division (divide-by-two is commonly used), thus the chip frequency drops significantly, leading to greater performance degradation. Although the dynamic PLL configuration may achieve more fine-grained frequency adjustment, the PLL adjustment needs a certain lock time, making the method unfavorable for fast frequency adjustment. The published clock stretching circuits have complex structure, generally achieve multiphase clock generation through DLL (Delay-Locked Loop) and have more precise delay phase control, but cost more area and are too complex which are unsuitable for the embedded low power chips.